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32mx64 bits pc133 sdram unbuffere d dimm based on 16mx8 sdram with lvttl, 4 banks & 4k refresh hym71v633201 h - series this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits describe d. no patent licenses are implied. rev. 1.1/dec. 9 9 ? 199 9 hyundai micro electronics description the hyundai hym71v633201 h - series are 32mx64bits synchronous dram modules. the modules are composed of sixteen 16mx8bit cmos synchronous drams in 400mil 54pin tsop - ii package, one 2kbit eeprom in 8pin tssop package on a 168pin glass - epoxy pr inted circuit board. one 0.22uf and one 0.0022uf decoupling capacitors per each sdram are mounted on the pcb. the hym71v633201 h - series are dual in - line memory modules suitable for easy interchange and addition of 256mbytes memory. the hym71v633201 h - seri es are offering fully synchronous operation referenced to a positive edge of the clock. all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. features p c133/pc100mhz support 168pin sdram unbuffered dimm serial presence detect with eeprom 1.375 ? (34.93mm) height pcb with double sided components single 3.3 0.3v power supply all devices pins are compatible with lvttl interface data mask function by d qm sdram internal banks : four banks module bank : two physical bank auto refresh and self refresh 4096 refresh cycles / 64ms programmable burst length and burst type - . 1, 2, 4, 8 or full page for sequential burst - . 1, 2, 4 or 8 for interleave burst programmable /cas latency - . 2, 3 clocks ordering information part no. max. frequency internal bank ref. power sdram package plating hym71v633201th - 75 133mhz normal hym71v633201lth - 75 133mhz 4 banks 4k low power tsop - ii gold
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 2 pin description p in n ame d escription ck0 ~ck3 clock inputs the system clock input . all other inputs are registered to the sdram on the rising edge of clk. cke0 , cke1 clock enable c ontrols internal clock signal and when deactivated, the sdram will be one of the states a mong power down, suspend or self refresh. /s0 ~ /s3 chip select enables or disables all inputs except ck, cke and dqm. ba0, ba1 sdram bank address select bank to be activated during /ras activity. select bank to be read/written during /cas activity a0~a1 1 address inputs row address : ra0~ra11, column address : ca0~ca9 auto - precharge flag : a10 /ras row address strobe /ras define the operation. refer to the function truth table for details. /cas column address strobe /cas define the operation. refer to t he function truth table for details. /we write enable /we define the operation. refer to the function truth table for details. dqm0~dqm7 data input/output mask controls output buffers in read mode and masks input data in write mode. dq0~dq63 data input/ output multiplexed data input/output pins vcc power supply (3.3v) power supply for internal circuits and input/output buffers vss ground ground scl spd clock input serial presence detect clock input sda spd data input/output serial presence detect data i nput /o utput sa0~sa2 spd address input serial presence detect address i nput wp write protect for spd write protect for serial presence detect on dimm nc no connect no connect or don ? t use
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 3 pin assignments front side back side front side back side pin no. name pin no. name pin no. name pin no. name 1 vss 85 vss 41 vcc 125 ck1 2 dq0 86 dq32 42 ck0 126 nc 3 dq1 87 dq33 43 vss 127 vss 4 dq2 88 dq34 44 nc 128 cke0 5 dq3 89 dq35 45 /s2 129 nc 6 vcc 90 vcc 46 dqm2 130 dqm6 7 dq4 91 dq36 47 dqm3 131 dqm7 8 dq5 92 dq37 48 nc 132 nc 9 dq6 93 dq38 49 vcc 133 vcc 10 dq7 94 dq39 50 nc 134 nc 51 nc 135 nc architecture key 52 nc 136 nc 11 dq8 95 dq40 53 nc 137 nc 12 vss 96 vss 54 vss 138 vss 13 dq9 97 dq41 55 dq16 139 dq48 14 dq10 98 dq42 56 dq17 140 dq49 15 dq11 99 dq43 57 dq18 141 dq50 16 dq12 100 dq44 58 dq19 142 dq51 17 dq13 101 dq45 59 vcc 143 vcc 18 vcc 102 vcc 60 dq20 144 dq52 19 dq14 103 dq46 61 nc 145 nc 20 dq15 104 dq47 62 nc 146 nc 21 nc 105 nc 63 nc 147 nc 22 nc 106 nc 64 vss 14 8 vss 23 vss 107 vss 65 dq21 149 dq53 24 nc 108 nc 66 dq22 150 dq54 25 nc 109 nc 67 dq23 151 dq55 26 vcc 110 vcc 68 vss 152 vss 27 /we 111 /cas 69 dq24 153 dq56 28 dqm0 112 dqm4 70 dq25 154 dq57 29 dqm1 113 dqm5 71 dq26 155 dq58 30 /s0 114 nc 72 dq 27 156 dq59 31 nc 115 /ras 73 vcc 157 vcc 32 vss 116 vss 74 dq28 158 dq60 33 a0 117 a1 75 dq29 159 dq61 34 a2 118 a3 76 dq30 160 dq62 35 a4 119 a5 77 dq31 161 dq63 36 a6 120 a7 78 vss 162 vss 37 a8 121 a9 79 ck2 163 ck3 38 a10/ap 122 ba0 80 nc 164 nc 39 ba1 123 a11 81 wp 165 sa0 40 vcc 124 vcc 82 sda 166 sa1 83 scl 167 sa2 voltage key 84 vcc 168 vcc
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 4 block diagram note : 1. the serial resistor values of dqs are 10 ohms.
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 5 serial presence detect byte function function value numb er described - 75 - 75 note byte0 # of bytes written into serial memory at module manufacturer 128 bytes 80h byte1 total # of bytes of spd memory device 256 bytes 08h byte2 fundamental memory type sdram 04h byte3 # of row addresses on this assembly 1 2 0 c h 1 byte4 # of column addresses on this assembly 10 0 a h byte5 # of module banks on this assembly 2 bank s 0 2 h byte6 data width of this assembly 64 bits 4 0 h byte7 data width of this assembly (continued) - 00h byte8 voltage interface standard of this assembly lvttl 01h byte9 sdram cycle time @ /cas latency=3 7.5ns 75h byte10 access time from clock @ /cas latency=3 5.4ns 54h byte11 dimm configuration type none 0 0 h byte12 refresh rate/type 15.625 m s / self refresh supported 80h byte13 primary s dram width x8 08 h byte14 error checking sdram width none 0 0 h byte15 min imum clock delay back to back random column address t ccd = 1 clk 01h byte16 burst lengths supported 1,2,4,8,full page 8fh 2 byte17 # of banks on each sdram device 4 banks 0 4 h byte18 sdram device attributes, cas # latency /cas latency=2,3 0 6 h byte19 sdram device attributes, cs # latency /cs latency=0 01h byte20 sdram device attributes, write latency /we latency=0 01h byte21 sdram module attributes neither buffered nor reg istered 00 h byte22 sdram device attributes , general +/ - 10% voltage tolerance, burst read single bit write, precharge all, auto precharge, early ras precharge 0 e h byte23 sdram cycle time @ /cas latency=2 10ns a0h byte2 4 access time from clock @ /cas l atency= 2 6ns 60h byte2 5 sdram cycle time @ /cas latency= 1 - 00h byte2 6 access time from clock @ /cas latency= 1 - 00h byte2 7 minimum row precharge time (trp) 20ns 14h byte2 8 minimum row active to row active delay (trrd) 15ns 0fh byte2 9 minimum /ra s to /cas delay (trcd) 20ns 14h byte 30 minimum /ras pulse width (tras) 45ns 2dh byte 31 module bank density 128mb 20h byte 32 command and address signal input setup time 1.5ns 15h byte 33 command and address signal input hold time 0.8ns 08h byte 34 d ata signal input setup time 1.5ns 15h byte 35 data signal input hold time 0.8ns 08h byte 36 ? 61 superset information (may be used in future) - 00h byte 62 spd revision intel spd 1.2 12h 3, 8 byte 63 checksum for bytes 0~62 - b0h byte 64 manufacture r jedec id code hyundai jedec id ad h byte 65 ~71 ....manufacturer jedec id code unused ff h byte 72 manufacturing location hei (korea) hea (united states) heu (europe) 0 1 h 02h 03h
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 6 continued byte function function value number described - 75 - 75 note byte 73 manufacturer ? s part number (component) 7 (sdram) 37 h 4, 5 byte 74 manufacturer ? s part number (128mb based) 1 31 h 4, 5 byte 75 manufacturer ? s part number (voltage interface) v (3.3v, lvttl) 56 h 4, 5 byte 76 manufacturer ? s part number (data widt h) 6 36 h 4, 5 byte 77 ....manufacturer ? s part number (data width) 3 33 h 4, 5 byte 78 manufacturer ? s part number (memory depth) 3 33h 4, 5 byte 79 ? .manufacturer ? s part number (memory depth) 2 32h 4, 5 byte 80 manufacturer ? s part number (refresh) 0 (4k refr esh) 30 h 4, 5 byte 81 manufacturer ? s part number (internal banks) 1 (4 banks) 31h 4, 5 byte 82 manufacturer ? s part number (package type) t (tsopii) 54h 4, 5 byte 83 manufacturer ? s part number (module type) h (x8 based) 48 h 4, 5 byte 84 manufacturer ? s part number (hyphen) - (hyphen) 2d h 4, 5 byte 85 manufacturer ? s part number (min. cycle time) 7 37h 4, 5 byte 86 ....manufacturer ? s part number (min. cycle time) 5 35h 4, 5 byte 87 ~90 manufacturer ? s part number blanks 20h 4, 5 byte91 revision code (for com ponent) process code - 4, 6 byte92 ....revision code (for pcb) process code - 4, 6 byte93 manufacturing date work week - 3, 6 byte94 ....manufacturing date year - 3, 6 byte95 ~98 assembly serial number serial number - 6 byte99 ~125 manufacturer specific data (may be used in future) none 00h byte126 reserved refer to note9 64h 7, 8, 9 byte127 reserved refer to note9 f 7 h 7, 8, 9 byte128 ~256 unused storage locations - 00h note: 1. the bank address is excluded. 2. 1,2,4,8 for inte rleave burst type 3. bcd adopted. 4. ascii adopted. 5. basically hyundai writes part no. except for ` hym ` in byte 73 - 90 to use the limited 18 bytes from byte 73 to 90 efficiently. 6. not fixed but dependent. 7. clk0~clk3 connecte d on the dimm, tbd junction temp, cl2(3) support, intel defined concurrent auto precharge support 8. refer to most recent version intel and jedec spd specification. 9. these values are applied to pc100 applicationsonly per intel pc sdram specific ation
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 7 absolute maximum ratings p arameter symbol rating unit ambient temperature ta 0 ~ 70 c storage temperature tstg - 55 ~ 125 c voltage on any pin relative to vss vin, vout - 1.0 ~ 4.6 v voltage on vdd relative to vss vdd, vddq - 1.0 ~ 4.6 v shor t circuit output current ios 50 ma power dissipation pd 8 w soldering temperature time tsolder 260 10 c sec note : operation at above absolute maximum can adversely affect device reliability. dc operating condition (ta = 0 to 70 c ) p arameter symbol min typ. max unit note power supply voltage vcc 3.0 3.3 3.6 v 1 input high voltage vih 2.0 3.0 vcc + 0.3 v 1, 2 input low voltage vil ? 0.3 0 0.8 v 1, 3 note : 1. all voltage are referenced to vss = 0v. 2. vih (max) is acceptable 5.6v ac pulse width with 3ns of duration. 3. vil (min) is acceptable ? 2.0v ac pulse width with 3ns of duration. ac operating condition (ta = 0 to 70 c , vdd = 3.3 0.3v, vss = 0v) p arameter symbol value unit ac input high / low level voltage vih / vil 2.4 / 0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement cl *note pf note : *. output load to measure access time is equivalent to two ttl gates and one capacitor (50pf). for details, refer to ac/dc output circuit.
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 8 capacitance (ta = 25 c , f = 1mhz) p arameter pin symbol min max typ. unit ck0~ ck3 cin1 35 40 - pf cke0, cke1 cin2 45 50 - pf /s0~ /s3 cin3 25 35 - pf a0~a11, ba0, ba1 cin4 70 85 - pf /ras, /cas, /we cin5 70 85 - pf input capacitance dqm0~dqm7 cin6 15 20 - pf data input/output capacitance dq0~dq63 ci/o 10 20 - pf output load circuit
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 9 dc characteristics i (ta = 0 to 70 c , vdd = 3.3 0.3v) p arameter symbol min max unit note input leakage current ili - 16 16 ua 1 output leakage current ilo - 1 1 ua 2 output high voltage voh 2.4 - v ioh = - 4ma output low voltage vol - 0.4 v iol = +4ma note : 1. vin = 0 to 3.6v. all other pins are not tested under vin = 0v. 2. dout is disabled. vout = 0 to 3.6v. dc characteristics ii (ta = 0 to 70 c , vdd = 3.3 0.3v, vss = 0v) speed p arameter symbol test condition - 75 unit note operating current idd1 burst length = 1, one bank active trc 3 trc(min), iol = 0ma 1200 ma 1 idd2p cke vil(max), tck = min 32 ma pre charge standby current in power down mode idd2ps cke vil(max), tck = 24 ma idd2n cke 3 vih(min), /cs 3 vih(min), tck = min input signals are changed one time du ring 2clks. all other pins 3 vdd ? 0.2v or 0.2v 320 ma precharge standby current in non power down mode idd2ns cke 3 vih(max), tck = input signals are stable. 160 ma idd3p cke vil(max), tck = min 112 ma active standby current in power down mode idd3ps cke vil(max), tck = 112 ma idd3n cke 3 vih(min), /cs 3 vih(min), tck = min input signals are changed one time during 2clks. all other pins 3 vdd ? 0.2v or 0.2v 640 ma active standby current in non power down mode idd3ns cke 3 vih(max), tck = input signals are stable. 640 ma cl = 3 1760 burst mode operating current idd4 tck 3 tck(min), iol = 0ma all banks active cl = 2 1600 ma 1 auto refresh current idd5 trrc 3 trrc(min), all banks active 4800 ma 2 32 ma 3 self refresh current idd6 cke 0.2v 12.8 ma 4 note : 1. idd1 and idd4 depend on output loading and cycle rates. specified values are measured with the output open. 2. min. of trrc (refresh /ras cycle time) is shown at ac characteristics ii. 3. hym71v633201th - 75 4. hym71v633201lth - 75
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 10 ac charact eristics i (ac operating conditions unless otherwise noted) - 75 p arameter symbol min max unit note /cas latency = 3 tck3 7.5 system clock cycle time /cas latency = 2 tck2 10 1000 ns clock high pulse width tchw 2.5 - ns i clock low pulse widt h tclw 2.5 - ns i /cas latency = 3 tac3 - 5.4 access time from clock /cas latency = 2 tac2 - 6 ns 2 data - out hold time toh 2.7 - ns data - input setup time tds 1.5 - ns 1 data - input hold time tdh 0.8 - ns 1 address setup time tas 1.5 - ns 1 addres s hold time tah 0.8 - ns 1 cke setup time tcks 1.5 - ns 1 cke hold time tckh 0.8 - ns 1 command setup time tcs 1.5 - ns 1 command hold time tch 0.8 - ns 1 clk to data output in low - z time tolz 1 - ns /cas latency = 3 tohz3 2.7 5.4 ns clk to data output in high - z time /cas latency = 2 tohz2 3 6 ns note : 1. assume tr / tf (input rise and fall time ) is 1ns . if tr & tf > 1ns, then [(tr+tf)/2 - 1]ns should be added to the parameter 2. access times to be measured with input signals of 1v/ns edge rate , from 0.8v to 2.0v . if tr > 1ns, then (tr/2 - 0.5)ns should be added to the parameter
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 11 ac characteristics ii - 75 p arameter symbol min max unit note operation trc 65 /ras cycle time auto refresh trrc 65 - ns /ras to /cas delay trcd 20 - ns /ras active time tras 45 100k ns /ras precharge time trp 20 - ns /ras to /ras bank active delay trrd 15 - ns /cas to /cas delay tccd 1 - clk write command to data - in delay twtl 0 - clk data - in to precharge command tdpl 2 - clk data - in to active command tdal 5 - clk dqm to data - out hi - z tdqz 2 - clk dqm to data - in mask tdqm 0 - clk mrs to new command tmrd 2 - clk /cas latency = 3 tproz3 3 - precharge to data output hi - z /cas latency = 2 tproz2 2 - clk power down exit time tpde 1 - clk self refresh exit time tsre 1 - clk 1 refresh time tref - 64 ms note : 1. a new command can be given trrc after self refresh exit.
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 12 operating option table hym71v633201(l)th - 75 /cas latency trcd tras trc trp tac toh 133mhz (7.5ns) 3clk s 3clks 6clks 9clks 3clks 5.4ns 2.7ns 125mhz (8.0ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz (10.0ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns command truth table cken - 1 cken /cs /ras /cas /we dqm addr a10/ ap ba note mode register set h x l l l l x op code h x x x no operation h x l h h h x x bank active h x l l h h x ra v read l read with autoprecharge h x l h l h x ca h v write l write with autoprecharge h x l h l l x ca h v precharge all banks h x precharge selected bank h x l l h l x x l v burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x entry h l l l l h x h x x x self refresh exit l h l h h h x x 1 h x x x entry h l l h h h x h x x x precharge power down exit l h l h h h x x h x x x entry h l l v v v x clock suspend exit l h x x x note : 1. existing self refresh occurs by asynchronously bringing cke from low to high. 2. x = don ? t care, h = logic high, l = logic lo w, ba = bank address, ca = column address, op code = operand code, nop = no operation
pc133 sdram unbuffered dimm hym71v633201 h - series rev. 1.1/dec.99 13 package dimensions

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